
read_verilog  /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v
analyze -library WORK -format verilog {/net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/or1200-master/rtl/verilog/or1200_fpu.v}
elaborate or1200_fpu -architecture verilog -library DEFAULT
link
load_upf /net/plato.ee.Virginia.edu/misan0/users/vv8dn/synopsys/ASIC_project/dc/ref/models/design3.upf

set_operating_conditions TYPICAL
set_voltage 1.2 -object_list VDD
set_voltage 0.75 -object_list VDDT
set_voltage 0 -object_list VSS

check_design
source ../source/constr.sdc		
compile_ultra -exact_map
report_area
report_constraint
report_timing
write -hierarchy -format verilog -output ../results/or1200_fpu_dc.v
save_upf ../results/design_dc.upf
